1. Field of the Invention
This invention relates to a gate array device, and more particularly to reduction in the voltage in a gate array device.
2. Description of the Related Art
Conventionally, requirements for lowering an operation voltage of an integrated circuit (IC) have become stronger with the formation of elements of even greater miniaturization and chips of lower power consumption. As the voltage lowering method, a method of previously lowering a voltage (from 5V to 3.3V) supplied from the exterior of the IC is used.
In the IC chip, it is seldom that the operation frequencies of circuit portions are set at the same frequency, and a circuit portion for effecting the high-speed operation and a circuit portion for effecting the low-speed operation are formed on the same chip. Since the operation speed and power of the circuit vary in proportion to the power source voltage, it is most efficient and ideal to supply an operation voltage corresponding to the operation speed to the circuit.
However, the above method has a defect that the power source system may become complicated and is not practical. In practice, all of the circuits are operated at a constant voltage by use of a single power source, and particularly, in an ASIC such as a gate array designed according to the user's specification, it is a common practice to operate them by a single power source.
With the conventional system using a single power source, two or more power source voltages are necessary and the power source voltage supplying system becomes complicated when an IC operated on an operation voltage of 5V and an IC operated on an operation voltage of 3.3V are formed on one board (system). An interface for voltage conversion from 5V to 3.3V or from 3.3V to 5V must be provided between the ICs, and particularly, the design of the input and output sections of the chip operated on 3.3V becomes difficult.
In order to lower the power consumption of the chip, it may be best to lower the operation voltage for a circuit portion operated at a low speed since in this case the power consumption can be lowered without degrading the system performance. However, with the conventional method of using a single lowered operation voltage and supplying the lowered voltage to the chip, the operation speeds of all of the circuits are lowered according to reduction in the operation voltage and therefore the performance thereof will be degraded.
It is reported that, in order to solve the above problems, a voltage lowering circuit is incorporated in the custom products and only part of the circuits are operated on the lowered voltage. However, a method or system which is particularly effective for gate arrays in which the diffusion process is fixed and the circuit is determined according to the user's specification is not yet reported. Further, in the present custom products, a method of changing the operation voltage according to the operation speed of the circuit is not yet sufficiently completed and an effective method or system is not reported.